U.S. Pat. No. 3,997,882 granted to D. K. Goyal on Dec. 14, 1976, describes a charge coupled device (CCD) storage system having a fast clock which is used when performing read and write operations and a slow clock which is used for regenerating or refreshing the data in non-accessed storage cells. No mention is made of data buffering and no mention is made of using different operating speeds for different values of the I/O bus data transfer rate.
U.S. Pat. No. 4,084,154 granted to G. Panigrahi on Apr. 11, 1978, describes a charge coupled device (CCD) memory system wherein different sections of the CCD array are successively refreshed by bursts of clock pulses whereby at any given moment only a small number of the CCD registers are being refreshed. No significant mention is made of data buffering between the CCD system and an I/O bus and no mention is made of varying the CCD operating speed as a function of the effective I/O bus data transfer rate.
Section 5-3 (pages 214-219) entitled "Data Buffering With FIFO's" of a textbook by John B. Peatman entitled "Microcomputer-Based Design", copyright 1977, by McGraw Hill Book Co., describes in a general manner the use of First-In-First-Out (FIFO) storage devices for data buffering purposes. No specific mention is made of using a FIFO with a serial storage mechanism or of varying the operating speed of a serial storage mechanism.
U.S. Pat. No. 4,062,059 granted to S. Suzuki et al on Dec. 6, 1977, describes a more or less typical use of a FIFO mechanism in a data processor I/O system. No mention is made of serial storage type I/O devices or of variable speed I/O devices.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.